Verdict: Split — Reject phrase · Fund migration
Published June 2026
"Our product is quantum safe."
Claim class: Post-quantum security marketing — the broadest and most common claim in the market. Graded as the generic formulation, not any specific vendor or product.
Hardware reality
NOT DEMONSTRABLE
No hardware exists to test this claim. Any live "quantum resistance demo" validates nothing — treat it as a negative signal.
Signal integrity
PARTIAL
Mathematical evidence exists: security reductions, NIST competition, continuous cryptanalysis. Honest translation: "no known attack — yet." Proprietary algorithms that skipped public scrutiny are near-automatic reject.
Post-processing
WHERE IT DIES
Side-channel leakage, key management, hybrid-mode composition, classical dependencies. Most real "quantum safe" claims fail an audit for entirely classical reasons.
Threat relevance
REAL — ACT
Harvest-now-decrypt-later is the actual risk. Federal PQC deadline Dec 31, 2030. The threat model is sound even though the safety claim is untestable.
Business decision
SPLIT
Reject the phrase; fund the migration. The property you can actually buy: cryptographic agility — the ability to swap algorithms when cryptanalysis moves. Agility is a property. "Quantum safe" is a snapshot.
Verdict: False as stated — Nothing reaches the floor
Published August 2026
"Rack-mounted quantum systems now available for on-premises purchase deliver computational capability beyond classical simulation."
Claim class: Market-interpretation claim. Extends Scorecard 002 from two systems to the full commercially available field — seven systems, five modalities, three continents.
Evidence base: SAXON Q SXQ128 · Equal1 RacQ · Quantum Brilliance QB-QDK2.0 · AQT IBEX Q1 · AQT LYNX · ORCA PT-1/PT-2 · Quandela Belenos (MosaiQ-12). Scored under the Hardware Claims Rubric v1 on Effective Computational Width under each architecture's binding constraint — because circuit width and inter-core coupling, the standing test from 002, are the right variables for multi-core solid-state systems and the wrong ones for trapped-ion, sampling-photonic, and probabilistic-photonic machines.
Hardware reality
REAL — SCOPED
All seven systems exist, ship, and rack-mount; several are independently operated by national laboratories and supercomputing centres, which is stronger evidence than any vendor claim. Width does not survive. ECW across the entire surveyed field runs from 2 to approximately 15 qubits. The lower band of the classical simulation floor is 30. No system is within a factor of two of it, and none enters the contested 30–50 band.
Signal integrity
PARTIAL — ASYMMETRIC
Two of seven publish a two-qubit gate fidelity. AQT publishes the most complete record in the survey — error bars and min/max across the register — and is scored accordingly. The remainder publish partial figures or none. One vendor-versus-third-party discrepancy logged (AQT IBEX Q1: vendor 98.7%, third-party listings 97.7% and 98.85%; vendor figure used). No vendor publishes end-to-end wall-clock for a named workload.
Post-processing
WHERE IT DIES
Every system sits inside the range where exact classical simulation is instantaneous, so no output requires the quantum hardware to have produced it. Architecture-specific costs land on the user: SWAP routing on constrained topologies, shot overhead on probabilistic linear-optical gates, repetition on sampling machines, inter-core orchestration on multi-core designs. No vendor in the survey publishes a quantum-ablation baseline.
Threat relevance
NONE — PROCUREMENT RISK
No cryptographic implication anywhere in the survey and no movement on any PQC migration date. Two to fifteen physical qubits is not a point on the RSA-2048 curve. The live risk is procurement: capital and headcount committed against a utility reading the hardware does not support.
Business decision
SPLIT
Reject the utility claim. Fund the toolchain. The category is a training and integration purchase and on those terms defensible: hybrid orchestration rehearsal, variational-loop engineering at real shots-per-second, and — for the sovereignty-constrained buyer — data residency cloud access cannot provide. The honest alternative stands: at these widths a classical simulator teaches the same toolchain more cheaply and without hardware noise.
Three findings a reader can check without trusting us:
— Quandela's performance multipliers are 2n. "4,000× more computing power" at 12 qubits and "16 million-fold" at 24 are 212 = 4,096 and 224 = 16,777,216. That is the dimension of the state space, which is the quantity that sets classical simulation cost — not a measured result. Scored as a units finding, not a disclosure failure: the qubit counts themselves are stated plainly and accurately.
— The trapped-ion decoherence criticism is wrong and is rejected here. Hyperfine coherence-to-gate-time ratios reach ~106 against ~103 for superconducting. Trapped ions are the least coherence-limited modality in the survey. The real constraint is absolute wall-clock throughput, and the routing tax scored against Equal1 does not transfer to an all-to-all architecture.
— Quantum Brilliance publishes no performance figures for QDK2.0. No qubit count, gate fidelity, or coherence in vendor or partner material. The only peer-reviewed figure describes the prior-generation QB-QDK as a two-qubit system. ECW is left open at the upper end rather than estimated.
The standing test, revised: score every rack-scale entrant on Effective Computational Width under its own binding constraint, published as a range with assumptions, and on whether the headline names a quantity addressable in a single circuit. A machine that advertises a total it cannot address as one register has reported a chassis inventory. A machine that advertises a multiplier equal to the dimension of its state space has reported how hard it is to simulate, which is not the same as what it computes.
Kill conditions: a single addressable register above 30 qubits with circuit structure stated · demonstrated inter-core composition where a headline is scored AGGREGATE · 2Q fidelity ≥ 99.9% sustained across the full claimed register · end-to-end wall-clock for a named workload at a stated accuracy target (trapped-ion entries) · a named workload inside the sampling class where a current classical sampler fails (sampling architectures) · a quantum-ablation baseline · disclosure of any figure recorded UNDISCLOSED.
OPEN ITEMS · INFERRED: SAXON inter-core coupling · Equal1 linear topology · AQT effective width derived from published Quantum Volume · UNDISCLOSED: SAXON 2Q fidelity · Quantum Brilliance qubit count, fidelity, coherence · AQT LYNX qubit count and fidelities · Quandela per-gate success probability and heralding rate · DISCREPANCY: AQT IBEX Q1 2Q fidelity across sources · COMMENTARY: Quandela source and detector cryogenic temperatures · NOT RUN: ORCA problem-class match test — no utility verdict entered for this system beyond NON-COMPARABLE · PENDING: right of reply to all named vendors before findings are treated as settled.
ARTIFACT ·
Scorecard 005 (PDF)
·
Hardware Claims Rubric v1 (PDF)
· AQT IBEX Q1 & LYNX product documentation · Amazon Braket provider docs · Quantum Brilliance & Fraunhofer IAF announcements; arXiv:2312.11673 · ORCA PT-1/PT-2 product pages; arXiv:2409.13781 · Quandela Belenos product page & Product Catalogue v6 · SAXON Q & Equal1 specifications per Scorecard 002 · All cells captured August 2026
Superseded by 005 · Verdict stands: False as stated
Published August 2026 · Superseded August 2026
SUPERSEDED BY SCORECARD 005 · August 2026. This entry graded the rack-scale utility claim against a two-system evidence base. Scorecard 005 grades the same claim against seven systems across five modalities and replaces the standing test with Effective Computational Width. The verdict is unchanged and the grades stand — both machines sit below the floor under either criterion. Retained in full because it is the record the correction was applied to. Read Scorecard 005 →
"Commercially available rack-scale quantum systems are useful for production workloads today."
Claim class: Market-interpretation claim — the reading buyers are taking from rack-mounted quantum general availability. Graded as the generic formulation, not as a review of any named vendor or product.
Evidence base: SAXON Q SXQ128 (NV-centre diamond, room temperature, wall outlet, 16 × 8-qubit cores) and Equal1 RacQ (silicon spin quantum dots, 0.3 K on-chip cryogenics, 6 qubits, GlobalFoundries 22FDX). Both machines are accurately described by their own published specifications. The failure is in the interpretation the market has placed on them.
Hardware reality
REAL — SCOPED
The machines exist, ship, and rack-mount. That part survives. The width does not: the largest circuit addressable as one coherent register is 8 qubits on SXQ128 and 6 on RacQ. The advertised 128 is sixteen disconnected eights. Thermal architecture is not the dividing line — both eliminate the facility requirement, though they do not impose the same operational burden.
Signal integrity
PARTIAL — ASYMMETRIC
Equal1 publishes 2Q fidelity (99.3% @ 200ns, interleaved). SAXON publishes 99.92% 1Q and omits 2Q entirely. Scored on non-identical criteria, no value inferred for the omission — but undisclosed 2Q fidelity is itself a finding, not a gap. 99.3% clears the ~99% surface-code threshold; clearing threshold is not affording it.
Post-processing
WHERE IT DIES
Neither headline number is addressable as a single register; the routing cost lands on the user. Four SWAPs on a linear 6-chain = 12 CNOTs of tax (0.99313 ≈ 91.2%, ~2.6µs of accumulated noise). Parallel sub-circuits are not a workaround but a different machine model: independent registers give throughput, not width. Inter-core transfer makes it a distributed quantum architecture — an open research problem, not a free feature of shared chassis.
Threat relevance
NONE — PROCUREMENT RISK
No cryptographic implication and no movement on any PQC migration date. Breaking RSA-2048 needs thousands of logical qubits; 6–8 physical qubits is not a point on that curve. The live risk is procurement: capital and headcount committed against a utility claim the hardware does not support.
Business decision
SPLIT
Reject "useful for production workloads." Fund the toolchain. This is a training purchase, not a compute purchase — and as a training purchase it is defensible. Note the honest alternative: at 6–8 qubits a classical simulator teaches the same toolchain more cheaply, minus the hardware noise. What the hardware adds is the integration and operations rehearsal — the quantum-placeholder step in a classical-hybrid workflow — not the qubits.
The standing test: score every rack-scale entrant on maximum coherent circuit width and inter-core coupling — not on the headline number. A machine that advertises a total it cannot address as one register has reported a chassis inventory, not a processor.
Kill conditions: demonstrated inter-core entangling links sufficient to compose registers · a single addressable register above the classical-simulation floor (threshold used: 40 qubits) · 2Q fidelity ≥ 99.9% sustained at that width, with coherence exceeding the SWAP depth the topology requires · a quantum-ablation baseline on a named production workload · disclosure of SAXON 2Q gate fidelity.
OPEN ITEMS · SAXON inter-core coupling recorded as INFERRED, pending vendor confirmation · Equal1 linear topology assumed for the SWAP arithmetic, marked INFERRED · SAXON 2Q fidelity UNDISCLOSED, no value inferred.
STATUS HISTORY · August 2026 — correction to a published kill condition. This scorecard set the classical-simulation threshold at 40 qubits addressable as one register. That threshold is clearable on paper by circuits that remain classically reproducible in fact: Clifford circuits are efficiently simulable at any width, and tensor-network methods run well past 40 at low entanglement. Replaced with a three-band criterion — at or below 30 unambiguously below the floor, 30–50 contested and requiring stated circuit structure, above 50 as one register at sufficient depth above the floor. See Scorecard 005 and the Hardware Claims Rubric v1. The original grade stands and the verdict is unaffected — both machines sit below either threshold. Correction is an addendum, not a replacement.
ARTIFACT ·
Scorecard 002 (PDF)
· SAXON Q SXQ128 & Equal1 RacQ public specifications · GlobalFoundries 22FDX · Gidney (2025) RSA-2048 resource estimates
Scorecard 003 · In review
Q3 2026
"Quantum advantage will be demonstrated in 2026."
Claim class: Milestone interpretation — an earnings-call assertion that partners will achieve the first examples of quantum advantage in 2026, supported by a hybrid quantum–HPC chemistry result (77-qubit QPU paired with the full Fugaku supercomputer on iron-sulfur cluster electronic structure), cited as evidence of "reliable tools for pharmaceutical discovery."
Under test: Quantum-ablation baseline (does the identical classical pipeline collapse without the QPU samples?), best-classical comparison on the same accuracy target, wall-clock decomposition, endpoint selection timing, and the claim graded against the vendor's own published definition of quantum advantage.
Data access, logged: The underlying run data is stated to be available on request. Request submitted [DATE]; no response received as of [DATE]. Recorded as an UNDISCLOSED evidence grade on every cell that depends on it. This is a fact about the documentation and carries no inference about the data, the result, or the reason for non-response.
Scoping consequence: without the raw data the quantum-ablation baseline cannot be computed independently, so any verdict this entry reaches will be scoped to what the published record supports. A hybrid quantum–HPC claim also inverts the comparison used elsewhere in this ledger — the classical partner is a supercomputer, not commodity hardware — and the classical floor in Scorecard 005 does not transfer. That procedure is being written before this entry is graded, not after.
Grades publish only after the tests run — the claim gets the same treatment ours did. No verdict is pre-announced.
IN PROGRESS · Primary sources: IBM/RIKEN publication · Q1 2026 earnings call transcript · IBM–Pasqal advantage definition white paper · Raw run data requested, no response logged
Verdict: Correction notice — Claim withdrawn
Published August 2026
Self-audit: HHL end-to-end execution on NISQ hardware.
Claim under review: End-to-end HHL executed on IBM Torino via the ancilla-free construction — an executability claim, not a utility claim. Depths near decoherence, 2-bit clock precision, hardware noise acknowledged. This was our claim.
Result: the claim does not survive its own falsification test. [INSERT: the specific finding — what test was run, what it showed, and which part of the published claim it removes.] The preprint remains available and is not withdrawn from the record; the claim it makes is withdrawn. Full breakdown published on the Firebringer Quantum channel.
What survives: [INSERT: the part of the work that holds — construction, method, or negative result.]
Why this entry exists: this is the third public falsification of our own published work, after the fourteen-bit ECDLP solve and the QCFT session analysis. The instrument that grades market claims has now been turned on its author three times, and three times the claim lost. That is the entire basis on which the other entries in this ledger should be read — not because self-criticism is a credential, but because a scorecard that has never returned an unwelcome verdict about its author has not been tested.
CONFLICT DISCLOSURE · This entry grades work by the author of the rubric under which it is graded. The finding is adverse to the author, which limits but does not eliminate the concern. Independent review of this entry is welcome and will be logged in status history if it changes the grade.
Scorecard 006 · Pending
Q4 2026
Falsification log: prior published claims, ECDLP and QCFT.
Entering the ledger: two further self-falsifications currently published as narrative rather than in scorecard form — the fourteen-bit ECDLP solve (falsified by randomized-data substitution into the classical post-processing, which also invalidated twenty months of extraction methodology) and the QCFT session analysis (five independent artifacts including a two-backend timeline merge, a decoder operating on compressed bytes, and significance testing that measured hardware drift).
Both are already public. This entry converts them into the same five-category form the vendor entries use, so the standard applied to others and the standard applied to us are legible side by side rather than across three sites.